1. Technical Field of the Invention
This disclosure relates to a semiconductor memory device and, more specifically, to a semiconductor memory device having an internal voltage generation circuit for selectively generating an internal voltage according to an external voltage level.
2. Description of the Related Art
In semiconductor memory devices for use in mobile apparatuses, low voltage operation is the most significant factor. The design of a low voltage semiconductor memory device varies according to the external voltage used. For example, if an external voltage is a high voltage, an internal voltage generation circuit is employed to lower the high voltage and the lowered voltage is used as an internal voltage. If an external voltage is already a low voltage, the external voltage is used directly as an internal voltage. Thus, designers manage basic database with two mask sets based on an external low voltage or an external high voltage.
A low/high voltage compatible semiconductor memory device is now described below with reference to FIG. 1.
Referring to FIG. 1, a first database 100 of a semiconductor memory device for a low voltage has a layout in which an external low voltage is bonded to an internal voltage pad 110, which is coupled to a chip internal circuit 120. An internal voltage generation circuit 130 of an active state, an internal voltage generation circuit 140 of a stand-by state, and a reference voltage generation circuit 150 are all disabled. On the other hand, a second database 200 of a semiconductor memory device for a high voltage has a layout in which an internal voltage pad 110 floats and an internal voltage generation circuit 130 of an active state, an internal voltage generation circuit 140 of a stand-by state, and a reference voltage generation circuit 150 are enabled to compare an external high voltage with a reference, thereby generating an internal voltage.
Independently managing the first and second database is troublesome and may cause an error in selection of database for revision. In addition, mask sets must be managed independently according to the first and second database, which leads to the disadvantage of high cost. Thus, there is a need for a semiconductor memory device which can simply manage databases and reduce a mask making expenditure.
The internal voltage generation circuits 130 and 140 stably generate an internal voltage depending on the variation of an external voltage and provide the internal voltage to the chip internal circuits 120. An internal voltage level may be slightly varied by the operation of a plurality of sense amplifiers disposed in a chip internal circuit such as, for example, a memory cell array block.
A conventional internal voltage generation circuit is now described below by reference to FIG. 2, in which an internal voltage generation circuit 130 of an active state is representatively illustrated.
Referring to FIG. 2, the internal voltage generation circuit 130 provides an external voltage VEXT to an internal voltage VINT by means of a PMOS transistor 138 which is responsive to an output of an NMOS transistor controlled by an output of an enable pulse generator 134. The internal voltage VINT is is compared with the reference voltage VREF by the comparator 132. An output of the comparator 132 controls the PMOS transistor 138, so that a feedback loop is established to provide the internal voltage VINT.
In the internal voltage generation circuit 130, a lowering of the internal voltage VINT may occur when a plurality of sense amplifiers in a memory cell array block 120′ operate at the same time. Unfortunately, the internal voltage generation circuit 130 is incapable of stably maintaining the level of the internal voltage VINT. Thus, there is a need for an internal voltage generation circuit which can stably generate an internal voltage.
Embodiments of the invention address this and other disadvantages of the conventional art.